Soc design 3: systemverilog features for rtl coding


Soc design 3: systemverilog features for rtl coding

MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English | Duration: 1 hour | Size: 408 MB
System Verilog Programming: Special Constructs for Design / RTL Coding in Systemverilog over Verilog

What Will I Learn?
Be able to use Systemverilog extended features for RTL Coding
Requirements
Know about basics of coding in Systemverilog or Verilog.
Be able to write simple Systemverilog Programs
Description
This is a short, intermediate level course in Systemverilog HDL and it covers only the few specific topic in it which are useful in design /RTL coding. The objective of this course is to teach Systemverilog extensions to Verilog for RTL design coding which are widely used in the VLSI industry.
Although,it is designed for learning SoC design coding rather than verification, verification engineers are also encouraged to enroll this, as all of them are useful in test-bench coding as well . This will teach below constructs.
Constants & Parameters
Parameterized Modules
Functions & Tasks
Enumeration
Typedef
Structure
Interfaces & Modports
Generate Statements
If you are an expert, or someone who is already writing full fledged systemverilog RTL design code, this course is NOT for you. Also, if you are beginner to Verilog or Systemverilog, this course will NOT teach the basics of programming for those HDLs.
To make this course effective for you, you must have the basic knowledge of either Verilog or Systemverilog. You should be able to write simple design and test bench programs in Verilog or Systemverilog, and simulate.
Who is the target audience?
Someone who is already familiar with Systemverilog programming
SoC Design engineers not familiar with Systemverilog specific features useful in RTL coding

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